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low skew, 1-to-2 differential-to- lvds fanout buffer ICS85411I idt ? / ics ? differential-to-lvds fanout buffer 1 ics85411ami rev. b november 7, 2007 g eneral d escription the ICS85411I is a low skew, high performance 1-to-2 differential-to-lvds f anout buffer and a member of the hiperclocks? family of high performance clock solutions from idt. the clk, nclk pair can accept most standard differential in- put levels.the ICS85411I is characterized to operate from a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ICS85411I ideal for those clock distribution applications demanding well defined per- formance and repeatability. f eatures ? two differential lvds outputs ? one differential clk, nclk clock input ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? maximum output frequency: 650mhz ? translates any single ended input signal to lvds levels with resistor bias on nclk input ? output skew: 25ps (maximum) ? part-to-part skew: 300ps (maximum) ? additive phase jitter, rms: 0.05ps (typical) ? propagation delay: 2.5ns (maximum) ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead free (rohs 6) packages b lock d iagram p in a ssignment ICS85411I 8-lead soic 3.90mm x 4.90mm x 1.37mm package body m package top view q0 nq0 q1 nq1 1 2 3 4 hiperclocks? ic s v dd clk nclk gnd 8 7 6 5 q0 nq0 q1 nq1 clk nclk
idt ? / ics ? differential-to-lvds fanout buffer 2 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 4 , 31 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 5d n gr e w o p. d n u o r g y l p p u s r e w o p 6k l c nt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 7k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 8v d d r e w o p. n i p y l p p u s e v i t i s o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
idt ? / ics ? differential-to-lvds fanout buffer 3 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer t able 3a. p ower s upply dc c haracteristics , v dd = 3.3v10%, t a = -40c to 85c t able 3b. d ifferential dc c haracteristics , v dd = 3.3v10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 7 9 . 23 . 33 6 . 3v i d d t n e r r u c y l p p u s r e w o p 0 5a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l cv d d v = n i v 3 6 . 3 =5a k l c nv d d v = n i v 3 6 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l cv d d v , 3 6 . 3 = n i v 0 =0 5 1 -a k l c nv d d v , v 3 6 . 3 = n i v 0 =5 -a v p p 1 e t o n ; e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0v d d 5 8 . 0 -v v : 1 e t o n l i . v 3 . 0 - n a h t s s e l e b t o n d l u o h s v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 3c. lvds dc c haracteristics , v dd = 3.3v10%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 7 4 25 2 34 5 4v m v d o e g n a h c e d u t i n g a m d o v 00 5v m v s o e g a t l o v t e s f f o 5 2 3 . 15 4 . 15 7 5 . 1v v s o e g n a h c e d u t i n g a m s o v 50 5v m i f f o e g a k a e l f f o r e w o p 0 2 -1 0 2 +a i d s o t n e r r u c t i u c r i c t r o h s t u p t u o l a i t n e r e f f i d 5 . 3 -5 -a m i s o t n e r r u c t i u c r i c t r o h s t u p t u o 5 . 3 -5 -a m v h o e g a t l o v h g i h t u p t u o 4 3 . 16 . 1v v l o e g a t l o v w o l t u p t u o 9 . 06 0 . 1v a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o contin uous current 10ma surge current 15ma package thermal impedance, ja 112.7c/w (0 lfpm) storage temperature, t stg -65c to 150c
idt ? / ics ? differential-to-lvds fanout buffer 4 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer t able 4. ac c haracteristics , v dd = 3.3v10% t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 6z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p 5 . 15 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 5 2s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 3s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r ) z h m 0 2 o t z h k 2 1 (5 0 . 0s p t r t / f e m i t l l a f / e s i r t u p t u oz h m 0 5 @ % 0 8 o t % 0 20 5 10 5 3s p c d oe l c y c y t u d t u p t u o z h m 0 0 5 > f6 44 5% f z h m 0 0 58 42 5% t a d e r u s a e m s r e t e m a r a p l l a? . e s i w r e h t o d e t o n s s e l n u z h m 0 5 6 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
idt ? / ics ? differential-to-lvds fanout buffer 5 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer a dditive p hase j itter input/output additive phase jitter @ 200mhz (12khz to 20mhz) = 0.05ps typical 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m 500m the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
idt ? / ics ? differential-to-lvds fanout buffer 6 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer p arameter m easurement i nformation d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx nqx lvds 3.3v10% power supply +? float gnd v dd p art - to -p art s kew v cmr cross points v pp gnd clk nclk v dd p ropagation d elay o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v od t sk(o) qx qy o utput s kew t pd nqx nqy q0, q1 nq0, nq1 clk nclk t sk(pp) part 1 part 2 qx qy nqx nqy t pw t period t pw t period odc = x 100% o utput d uty c ycle /p ulse w idth /p eriod q0, q1 nq0, nq1 d ifferential o utput v oltage s etup ? ? ? 100 out out lv d s dc input v od / v od v dd
idt ? / ics ? differential-to-lvds fanout buffer 7 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer p ower o ff l eakage s etup o ffset v oltage s etup o utput s hort c ircuit c urrent s etup d ifferential o utput s hort c ircuit c urrent s etup out out lv d s dc input ? ? ? v os / v os v dd out out lv d s dc input ? i osd v dd out lv d s dc input ? i os ? i osb v dd out lv d s ? i off v dd
idt ? / ics ? differential-to-lvds fanout buffer 8 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd r ecommendations for u nused o utput p ins o utputs : lvds all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, there should be no trace attached.
idt ? / ics ? differential-to-lvds fanout buffer 9 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 2a. h i p er c lock s clk/nclk i nput d riven by idt h i p er c lock s lvhstl d river examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 2a, the input termination applies for idt hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
idt ? / ics ? differential-to-lvds fanout buffer 10 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer lvds d river t ermination a general lvds interface is shown in figure 3. in a 100 differential transmission line environment, lvds drivers require a matched load termination of 100 across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. f igure 3. t ypical lvds d river t ermination r1 100 3.3v 100 ohm differential transmission line 3.3v + - lvds
idt ? / ics ? differential-to-lvds fanout buffer 11 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS85411I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS85411I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 10% = 3.63v, which gives worst case results. ? power (core) max = v dd_max * i dd_max = 3.63v * 50ma = 181.5mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3c/w per table 5 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.182w * 103.3c/w = 103.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 5. t hermal r esistance ja for 8-l ead soic, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? differential-to-lvds fanout buffer 12 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer r eliability i nformation t ransistor c ount the transistor count for ICS85411I is: 636 t able 6. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? differential-to-lvds fanout buffer 13 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer p ackage o utline - m s uffix for 8 l ead soic t able 7. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
idt ? / ics ? differential-to-lvds fanout buffer 14 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 8. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i m a 1 1 4 5 8 s c ii a 1 1 4 5 8c i o s d a e l 8e b u tc 5 8 o t c 0 4 - t i m a 1 1 4 5 8 s c ii a 1 1 4 5 8c i o s d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i m a 1 1 4 5 8 s c il i a 1 1 4 5 8c i o s " e e r f d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l i m a 1 1 4 5 8 s c il i a 1 1 4 5 8c i o s " e e r f d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? differential-to-lvds fanout buffer 15 ics85411ami rev. b november 7, 2007 ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b c 3 t3 8 1 1 v d e g n a h c d d . t e e h s a t a d t u o h g u o r h t % 0 1 o t % 5 m o r f v d e g n a h c - e l b a t s c i t s i r e t c a r a h c c d s d v l d o m o r f e g n a r . x a m v m 4 5 4 / . n i m v m 7 4 2 o t . x a m v m 0 6 3 / . n i m v m 0 0 2 d e g n a h c v d o . x a m v m 0 5 o t . x a m v m 0 4 m o r f v d e g n a h c s o . x a m v m 5 7 5 . 1 / . n i m v m 5 2 3 . 1 o t . x a m v m 5 7 3 . 1 / . n i m v m 5 2 1 . 1 m o r f d e g n a h c v s o . x a m v m 0 5 o t . x a m v m 5 2 m o r f d e d d a . s n i p t u p t u o d e s u n u r o f s n o i t a d n e m m o c e r d e d d a . s n o i t a r e d i s n o c r e w o p 96 0 / 5 2 / b4 , x 34 , 3. s e l b a t n i e r u t a r e p m e t d e t c e r r o c 7 0 / 7 / 1 1
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ICS85411I low skew, 1-to-2 differential-to-lvds fanout buffer

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